{"id":186,"date":"2020-04-05T07:03:44","date_gmt":"2020-04-05T07:03:44","guid":{"rendered":"https:\/\/temp.ashkerala.com\/?p=186"},"modified":"2020-04-05T07:03:44","modified_gmt":"2020-04-05T07:03:44","slug":"computer-architecture-mcq-4","status":"publish","type":"post","link":"https:\/\/temp.ashkerala.com\/?p=186","title":{"rendered":"Computer Architecture MCQ-4"},"content":{"rendered":"

Q.1 If the crystal oscillator is operating at 15 MHz, the PCLK output of 8284 is<\/strong>
(A) 2.5 MHz. (B) 5 MHz.
(C) 7.5 MHz. (D) 10 MHz.
Ans: (A)<\/strong><\/p>\n

Q.2 In which T-state does the CPU sends the address to memory or I\/O and the ALE signal for demultiplexing<\/strong>
(A) T1. (B) T2.
(C) T3. (D) T4.
Ans, During the first clocking period in a bus cycle, which is called T1, the address of
the memory or I\/O location is sent out and the control signals ALE, DT\/R\u0393\u00c7\u00d6 and IO\/M\u0393\u00c7\u00d6
are also output. Hence answer is (A).<\/strong><\/p>\n

Q.3 If a 1M\u251c\u00f91 DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no more than __________ of time must pass before another row is refreshed.<\/strong>
(A) 64 ms. (B) 4 ns.
(C) 0.5 ns. (D) 15.625 \u252c\u2561s .
Ans Answer is (B)<\/strong><\/p>\n

Q.4 In a DMA write operation the data is transferred<\/strong>
(A) from I\/O to memory. (B) from memory to I\/O.
(C) from memory to memory. (D) from I\/O to I\/O.
Ans A DMA writes operation transfers data from an I\/O device to memory. Hence
answer is (A).<\/strong><\/p>\n

Q.5 Which type of JMP instruction assembles if the distance is 0020 h bytes<\/strong>
(A) near. (B) far.
(C) short. (D) none of the above.
Ans The three byte near jump allows a branch or jump within \u252c\u2592 32K bytes. Hence
answer is (A).<\/strong><\/p>\n

Q.6 A certain SRAM has CS = 0 , WE = 0 and OE = 1. In which of the following modes this SRAM is operating<\/strong>
(A) Read (B) Write
(C) Stand by (D) None of the above
Ans For CS\u0393\u00c7\u00d6=WE\u0393\u00c7\u00d6=0, write operation. Hence answer is (B).<\/strong><\/p>\n

Q.7 Which of the following is true with respect to EEPROM?<\/strong>
(A) contents can be erased byte wise only.
(B) contents of full memory can be erased together.
(C) contents can be erased using ultra violet rays
(D) contents can not be erased
Ans Answer is (C).<\/strong><\/p>\n

Q.8 Pseudo instructions are basically<\/strong>
(A) false instructions.
(B) instructions that are ignored by the microprocessor.
(C) assembler directives.
(D) instructions that are treated like comments.
Ans Pseudo-instructions are commands to the assembler. All pseudo-operations start with a period. Pseudo-instructions are composed of a pseudo-operation which may be followed by one or more expressions. Hence answer is (C).<\/strong><\/p>\n

Q.9 Number of the times the instruction sequence below will loop before coming out of loop is
MOV AL, 00h
A1: INC AL
JNZ A1<\/strong>
(A) 00 (B) 01
(C) 255 (D) 256
Ans Answer is (D)<\/strong><\/p>\n

Q.10 What will be the contents of register AL after the following has been executed
MOV BL, 8C
MOV AL, 7E
ADD AL, BL<\/strong>
(A) 0A and carry flag is set (B) 0A and carry flag is reset
(C) 6A and carry flag is set (D) 6A and carry flag is reset
Ans, Result is 1,0A. Hence answer is (A).<\/strong><\/p>\n

Q.11 Direction flag is used with<\/strong>
(A) String instructions. (B) Stack instructions.
(C) Arithmetic instructions. (D) Branch instructions.
Ans The direction flag is used only with the string instructions. Hence answer is (A).<\/strong><\/p>\n

Q.12 Ready pin of a microprocessor is used<\/strong>
(A) to indicate that the microprocessor is ready to receive inputs.
(B) to indicate that the microprocessor is ready to receive outputs.
(C) to introduce wait states.
(D) to provide direct memory access.
Ans This input is controlled to insert wait states into the timing of the microprocessor.
Hence answer is (C).<\/strong><\/p>\n

Q.13 These are two ways in which a microprocessor can come out of Halt state.<\/strong>
(A) When hold line is a logical 1.
(B) When interrupt occurs and the interrupt system has been enabled.
(C) When both (A) and (B) are true.
(D) When either (A) or (B) are true.
Ans Answer is (A)<\/strong><\/p>\n

Q.14 In the instruction FADD, F stands for<\/strong>
(A) Far. (B) Floppy.
(C) Floating. (D) File.
Ans Adds two floating point numbers. Hence answer is (C).<\/strong><\/p>\n

Q.15 SD RAM refers to<\/strong>
(A) Synchronous DRAM (B) Static DRAM
(C) Semi DRAM (D) Second DRAM
Ans, Answer is (A)<\/strong><\/p>\n

Q.16 In case of DVD, the speed is referred in terms of n X (for example 32 X). Here, X refers to<\/strong>
(A) 150 KB\/s (B) 300 KB\/s
(C) 1.38 MB\/s (D) 2.4 MB\/s
Ans Answer is (C).<\/strong><\/p>\n

Q.17 Itanium processor of Intel is a<\/strong>
(A) 32 bit microprocessor. (B) 64 bit microprocessor.
(C) 128 bit microprocessor. (D) 256 bit microprocessor.
Ans The Itanium is a 64-bit architecture microprocessor. Hence answer is (B).<\/strong><\/p>\n

Q.18 LOCK prefix is used most often<\/strong>
(A) during normal execution. (B) during DMA accesses
(C) during interrupt servicing. (D) during memory accesses.
Ans LOCK is a prefix which is used to make an instruction of 8086 non-interruptable. Hence answer is (C).<\/strong><\/p>\n

Q.19 The Pentium microprocessor has______execution units.<\/strong>
(A) 1 (B) 2
(C) 3 (D) 4
Ans The Pentium microprocessor is organized with three execution units. One executes floating-point instructions, and the other two (U-pipe and V-pipe) execute integer instructions. Hence answer is (C).<\/strong><\/p>\n

Q.20 EPROM is generally erased by using<\/strong>
(A) Ultraviolet rays (B) infrared rays
(C) 12 V electrical pulse (D) 24 V electrical pulse
Ans The EPROM is erasable if exposed to high-intensity ultraviolet light for about 20 minutes or less. Hence answer is (A)<\/strong><\/p>\n

Q.21 Signal voltage ranges for a logic high and for a logic low in RS-232C standard are<\/strong>
(A) Low = 0 volt to 1.8 volt, high = 2.0 volt to 5 volt
(B) Low =-15 volt to \u0393\u00c7\u00f43 vol, high = +3 volt to +15 volt
(D) Low = +3 volt to +15 volt, high = -3 volt to -15 volt
(E) Low = 2 volt to 5.0 volt, high = 0 volt to 1.8 volt
Ans Answer is (B)<\/strong><\/p>\n

Q.22 The PCI bus is the important bus found in all the new Pentium systems because<\/strong>
(A) It has plug and play characteristics
(B) It has ability to function with a 64 bit data bus
(C) Any Microprocessor can be interfaced to it with PCI controller or bridge
(D) All of the above
Ans, Answer is (D).<\/strong><\/p>\n

Q.23 Which of the following statement is true?<\/strong>
(A) The group of machine cycle is called a state.
(B) A machine cycle consists of one or more instruction cycle.
(C) An instruction cycle is made up of machine cycles and a machine cycle is
made up of number of states.
(D) None of the above
Ans An instruction cycle consists of several machine cycles. Hence Answer is (B)<\/strong>.<\/p>\n

Q.24 8251 is a<\/strong>
(A) UART
(B) USART
(C) Programmable Interrupt controller
(D) Programmable interval timer\/counter
Ans The Intel 8251 is a programmable communication interface. It is USART.<\/strong><\/p>\n

Q.25 8088 microprocessor has<\/strong>
(A) 16 bit data bus (B) 4 byte pre-fetch queue
(C) 6 byte pre-fetch queue (D) 16 bit address bus
Ans The 8088 is a 16-bit microprocessor with an 8-bit data bus. The 16-bit address bus. Hence answer is (D).<\/strong><\/p>\n

Q.26 By what factor does the 8284A clock generator divide the crystal oscillator\u0393\u00c7\u00d6s output frequency?<\/strong>
(A) One (B) Two
(C) Three (D) Four
Ans When F\/C\u0393\u00c7\u00d6 is at logic 0; The oscillator output is steered through to the divideby- 3 counter. Hence answer is (c).<\/strong><\/p>\n

Q.27 The memory data bus width in Pentium is<\/strong>
(A) 16 bit (B) 32 bit
(C) 64 bit (D) None of these
Ans The Data bus width is 64 bits. Hence answer is (C).<\/strong><\/p>\n

Q.28 When the 82C55 is reset, its I\/O ports are all initializes as<\/strong>
(A) output port using mode 0 (B) Input port using mode 1
(C) output port using mode 1 (D) Input port using mode 0
Ans A RESET input to the 82C55 causes all ports to be set up as simple input ports using mode 0 operations. Hence answer is (D).<\/strong><\/p>\n

Q.29 Which microprocessor pins are used to request and acknowledge a DMA transfer?<\/strong>
(A) reset and ready (B) ready and wait
(C) HOLD and HLDA (D) None o these
Ans, The HOLD pin is an input that is used request a DMA action and the HLDA pin is an output that that acknowledges the DMA action. Hence answer is (C).<\/strong><\/p>\n

Q.30 Which of the following statement is false?<\/strong>
(A) RTOS performs tasks in predictable amount of time
(B) Windows 98 is RTOS
(C) Interrupts are used to develop RTOS
(D) Kernel is the one of component of any OS
Ans Operating systems, like Windows, defer many tasks and do not guarantee their execution in predictable time. Hence answer is (B).<\/strong><\/p>\n

Q.31 The VESA local bus operates at<\/strong>
(A) 8 MHz (B) 33 MHz
(C) 16 MHz (D) None of these
Ans The VESA local bus operates at 33 MHz. Hence answer is (B).<\/strong><\/p>\n

Q.32 The first modern computer was called_____________.<\/strong>
(A) FLOW-MATIC (B) UNIVAC-I
(C) ENIAC (D) INTEL
Ans, ENIAC (Electronic Numerical Integrator And Computer) was the first generalpurpose electronic computer. It was a Turing-complete, digital computer capable of being reprogrammed to solve a full range of computing problems. ENIAC was designed to calculate artillery firing tables for the U.S. Army’s Ballistic Research Laboratory. Hence answer is (c).<\/strong><\/p>\n

Q.33 Software command CLEAR MASK REGISTER in DMA<\/strong>
(A) Disables all channels.
(B) Enables all channels.
(C) None.
(D) Clears first\/last flip-flop within 8237.
Ans Enables all four DMA channels. Hence answer is (B).<\/strong><\/p>\n

Q.34 The first task of DOS operating system after loading into the memory is to use the file called___________.<\/strong>
(A) HIMEM.SYS (B) CONFIG.SYS
(C) AUTOEXEC.BAT (D) SYSTEM.INI
Ans, The first task of the DOS operating system, after loading into memory, is to use a file called the CONFIG.SYS file. This file specifies various drivers that load into the memory, setting up or configuring the machine for operation under DOS. <\/strong><\/p>\n

Q.35 If the programmable counter timer 8254 is set in mode 1 and is to be used to count six events, the output will remain at logic 0 for _____ number of counts<\/strong>
(A) 5 (B) 6
(C) 0 (D) All of the above
Ans. OUT continues for the total length of the count. Hence answer is (B).<\/strong><\/p>\n

Q.36 The flash memory is programmed in the system by 12 V programming pulse.<\/strong>
(A) TRUE (B) FALSE
Ans The flash memory device requires a 12V programming voltage to erase and write
new data. Hence answer is (A).<\/strong><\/p>\n

Q.37 A plug and play (PnP) interface is one that contains a memory that holds configuration information of the system.<\/strong>
(A) TRUE (B) FALSE
Ans Answer is (A)<\/strong>
Q.38 The accelerated graphics port (AGP) allows virtually any microprocessor to be interfaced with PCI bus via the use of bridge interface.<\/strong>
(A) TRUE (B) FALSE
Ans, this port probably will never be used for any devices other than the video card. Hence answer is (B).<\/strong><\/p>\n

Q.39 A Bus cycle is equal to how many clocking periods<\/strong>
(A) Two (B) Three
(C) Four (D) Six
Ans Typically, the bus-cycle of the 8086 and 8088 processors consist of four clock cycles or pulses. Thus, duration of a bus-cycle is = \u0393\u00c7\u00ff4*T\u0393\u00c7\u00d6. Hence Answer is (C).<\/strong><\/p>\n

Q.40 The time required to refresh a typical DRAM is<\/strong>
(A) 2 \u0393\u00c7\u00f4 4 us (B) 2 \u0393\u00c7\u00f4 4 ns
(C) 2 \u0393\u00c7\u00f4 4 ms (D) 2 \u0393\u00c7\u00f4 4 ps
Ans The capacitor Cs discharges through the internal resistance of the NMOS transistor T1. Typically Cs = 0.2 pF and the internal resistance Rin = 1010 ohms, so: Cs x Rin = 0.2 x 10-12 x 1010 x 103 ms = 2 ms So the typical refresh time interval is 2 ms. Hence Answer is (C).<\/strong>
\u00a0<\/p>\n

Q.41 The no. of address lines required to address a memory of size 32 K is<\/strong>
(A) 15 lines (B) 16 lines
(C) 18 lines (D) 14 lines
Ans 32K = 32 X 1024 bits = 25 X 210 = 2 15 Hence answer is ( A).<\/strong><\/p>\n

Q.42 The no. of wait states required to interface 8279 to 8086 with 8MHz clock are<\/strong>
(A) Two (B) Three
(C) One (D) None
Ans Two wait states used so that device can function with an 8 MHz. Hence answers is ( A).<\/strong><\/p>\n

Q.43 NMI input is<\/strong>
(A) Edge sensitive (B) Level sensitive
(C) Both edge and level triggered (D) edge triggered and level sensitive
Ans Non-maskable interrupt (NMI) is an edge \u0393\u00c7\u00f4triggered input that requests an interrupt on the positive edge (0 to 1 transition).<\/strong><\/p>\n

Q.44 Data rate available for use on USB is<\/strong>
(A) 12 Mbits per second (B) 1.5 Mbits per second
(C) Both (A) and (B) (D) No restriction
Ans Data transfer speeds are 12 Mbps for full speed operation and 1.5 Mbps for slow speed operation. Hence answer is (c).<\/strong><\/p>\n

Q.45 In 80186, the timer which connects to the system clock is<\/strong>
(A) timer 0 (B) timer 1
(C) timer 2 (D) Any one can be connected
Ans. Timer 2 is internal and clocked by the master clock. Hence answer is (c).<\/strong><\/p>\n

Q.46 Conversion of the +1000 decimal number into signed binary word results<\/strong>
(A) 0000 0011 1110 1000 (B) 1111 1100 0001 1000
(C) 1000 0011 1110 1000 (D) 0111 1100 0001 1000
Ans
1000 \/2 =>500 ->0
500\/2=>250->0
250\/2=>125->0
125\/2=>62->1
62\/2=>31->0
31\/2=>15->1
15\/2=>7->1
7\/2=>3->1
3\/2=>1->1
16 bit signed number is 1000,0011,1110,1000
Hence Answer is (C).<\/strong><\/p>\n

Q.47 What do the symbols [ ] indicate?<\/strong>
(A) Direct addressing (B) Register Addressing
(C) Indirect addressing (D) None of the above
Ans Answer is (C).<\/strong><\/p>\n

Q.48 SDRAM refers to<\/strong>
(A) static DRAM (B) synchronous DRAM
(C) sequential DRAM (D) semi DRAM
Ans, Answer is (B)<\/strong><\/p>\n

Q.49 Which pins are general purpose I\/O pins during mode-2 operation of the 82C55?<\/strong>
(A) PA0 \u0393\u00c7\u00f4 PA7 (B) PB0-PB7
(C) PC3-PC7 (D) PC0-PC2
Ans In mode 2 Port-A can be programmed to operate as bidirectional port. The mode-2 operation is only for Port-A. Hence Answer is (A)<\/strong><\/p>\n","protected":false},"excerpt":{"rendered":"

Q.1 If the crystal oscillator is operating at 15 MHz, the PCLK output of 8284 is (A) 2.5 MHz. (B) 5 MHz. (C) 7.5 MHz. (D) 10 MHz. Ans: (A) Q.2 In which T-state does the CPU sends the address to memory or I\/O and the ALE signal for demultiplexing (A) T1. (B) T2. (C)…<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"footnotes":""},"categories":[18],"tags":[],"class_list":["post-186","post","type-post","status-publish","format-standard","hentry","category-computer-architecture-and-organization"],"_links":{"self":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/posts\/186","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=186"}],"version-history":[{"count":0,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/posts\/186\/revisions"}],"wp:attachment":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=186"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=186"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=186"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}