{"id":191,"date":"2020-04-05T07:05:40","date_gmt":"2020-04-05T07:05:40","guid":{"rendered":"https:\/\/temp.ashkerala.com\/?p=191"},"modified":"2020-04-05T07:05:40","modified_gmt":"2020-04-05T07:05:40","slug":"computer-organization-mcq-2","status":"publish","type":"post","link":"https:\/\/temp.ashkerala.com\/?p=191","title":{"rendered":"Computer Organization MCQ -2"},"content":{"rendered":"

Q.16\u00a0 The addressing mode used in an instruction of the form ADD X Y, is<\/strong>
\u00a0(A) Absolute\u00a0 (B) indirect
\u00a0(C) index\u00a0\u00a0\u00a0\u00a0 (D) none of these
\u00a0
\u00a0Ans: C
\u00a0
Q.17\u00a0 If memory access takes 20 ns with cache and 110 ns with out it, then the ratio<\/strong> \u00a0
\u00a0 ( cache uses a 10 ns memory) is
\u00a0(A) 93%\u00a0 (B) 90%
\u00a0(C) 88%\u00a0 (D) 87%
\u00a0Ans: B \u00a0
\u00a0
Q.18\u00a0 In a memory-mapped I\/O system, which of the following will not be there?<\/strong>
\u00a0(A) LDA\u00a0 (B) IN
\u00a0(C) ADD\u00a0 (D) OUT
\u00a0
Ans: A \u00a0
\u00a0
Q.19\u00a0 In a vectored interrupt.<\/strong>
\u00a0(A) the branch address is assigned to a fixed location in memory.
\u00a0(B) the interrupting source supplies the branch information to the processor through an interrupt vector.
\u00a0(C) the branch address is obtained from a register in the processor
\u00a0(D) none of the above
\u00a0
\u00a0Ans: B
\u00a0
Q.20\u00a0 Von Neumann architecture is<\/strong>
\u00a0(A) SISD\u00a0 (B) SIMD
\u00a0(C) MIMD\u00a0 (D) MISD
\u00a0
\u00a0Ans: A
\u00a0
Q. 21 The circuit used to store one bit of data is known as<\/strong>
\u00a0(A) Encoder\u00a0\u00a0\u00a0 (B) OR gate
\u00a0(C) Flip Flop\u00a0 (D) Decoder
\u00a0
\u00a0Ans: C \u00a0
\u00a0
Q.22\u00a0 Cache memory acts between<\/strong>
\u00a0(A) CPU and RAM\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 (B) RAM and ROM
\u00a0(C) CPU and Hard Disk\u00a0 (D) None of these
\u00a0
\u00a0Ans: A \u00a0
\u00a0
Q.23\u00a0 Write Through technique is used in which memory for updating the data<\/strong>
\u00a0(A) Virtual memory\u00a0\u00a0\u00a0 (B) Main memory
\u00a0(C) Auxiliary memory\u00a0 (D) Cache memory
\u00a0
\u00a0Ans: D
\u00a0
Q.24\u00a0 Generally Dynamic RAM is used as main memory in a computer system as it<\/strong>
\u00a0(A) Consumes less power\u00a0\u00a0\u00a0\u00a0 (B) has higher speed
\u00a0(C) has lower cell density\u00a0 (D) needs refreshing circuitary
\u00a0
\u00a0Ans: B \u00a0
\u00a0
Q.25\u00a0 In signed-magnitude binary division, if the dividend is (11100)_2\u00a0 and divisor is (10011)_2 then the result is
_= Base<\/em><\/strong>
\u00a0 (A) (00100)_2
\u00a0 (B) (10100)_2
\u00a0 (C) (11001)_2
\u00a0 (D) (01100)_2
\u00a0
\u00a0Ans: B
\u00a0
Q.26\u00a0 Virtual memory consists of<\/strong>
\u00a0(A) Static RAM\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 (B) Dynamic RAM
\u00a0(C) Magnetic memory\u00a0 (D) None of these
\u00a0
\u00a0Ans: A
\u00a0
Q.27\u00a0 In a program using subroutine call instruction, it is necessary<\/strong>
\u00a0(A) initialise program counter \u00a0
\u00a0(B) Clear the accumulator
\u00a0(C) Reset the microprocessor
\u00a0(D) Clear the instruction register
\u00a0
\u00a0Ans: D \u00a0
\u00a0
Q.28\u00a0 A Stack-organised Computer uses instruction of<\/strong>
\u00a0(A) Indirect addressing\u00a0 (B) Two-addressing
\u00a0(C) Zero addressing\u00a0\u00a0\u00a0\u00a0\u00a0 (D) Index addressing
\u00a0
\u00a0Ans: C
\u00a0
Q.29\u00a0 If the main memory is of 8K bytes and the cache memory is of 2K words.\u00a0 It uses associative mapping.\u00a0 Then each word of cache memory shall be<\/strong>
\u00a0(A) 11 bits\u00a0 (B) 21 bits
\u00a0(C) 16 bits\u00a0 (D) 20 bits
\u00a0
\u00a0Ans: C
\u00a0
Q.30\u00a0 A-Flip Flop can be converted into T-Flip Flop by using additional logic circuit
_=Base<\/em><\/strong>
\u00a0 (A) D = T.Q_n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 (B)\u00a0\u00a0\u00a0 D = T’ \u00a0
\u00a0 (C) D = T.Q_n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 (D)\u00a0\u00a0\u00a0 D = T Exclusive Or Q_n \u00a0
\u00a0
\u00a0Ans: D<\/strong><\/p>\n","protected":false},"excerpt":{"rendered":"

Q.16\u00a0 The addressing mode used in an instruction of the form ADD X Y, is \u00a0(A) Absolute\u00a0 (B) indirect \u00a0(C) index\u00a0\u00a0\u00a0\u00a0 (D) none of these \u00a0 \u00a0Ans: C \u00a0 Q.17\u00a0 If memory access takes 20 ns with cache and 110 ns with out it, then the ratio \u00a0 \u00a0 ( cache uses a 10 ns…<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"footnotes":""},"categories":[18],"tags":[],"class_list":["post-191","post","type-post","status-publish","format-standard","hentry","category-computer-architecture-and-organization"],"_links":{"self":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/posts\/191","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=191"}],"version-history":[{"count":0,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/posts\/191\/revisions"}],"wp:attachment":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=191"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=191"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=191"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}