{"id":195,"date":"2020-04-05T07:07:14","date_gmt":"2020-04-05T07:07:14","guid":{"rendered":"https:\/\/temp.ashkerala.com\/?p=195"},"modified":"2020-04-05T07:07:14","modified_gmt":"2020-04-05T07:07:14","slug":"computer-organization-mcq-6","status":"publish","type":"post","link":"https:\/\/temp.ashkerala.com\/?p=195","title":{"rendered":"Computer Organization MCQ -6"},"content":{"rendered":"

Q.76\u00a0 An interface that provides I\/O transfer of data directly to and form the memory unit and peripheral is termed as \u00a0<\/strong>
\u00a0\u00a0 (A) DDA.\u00a0\u00a0 (B) Serial interface.
\u00a0\u00a0 (C) BR.\u00a0\u00a0\u00a0 (D) DMA.
\u00a0
\u00a0Ans: D
\u00a0
Q.77\u00a0 The 2s compliment form (Use 6 bit word) of the number 1010 is<\/strong>
\u00a0(A) 111100.\u00a0\u00a0 (B) 110110.
\u00a0(C) 110111.\u00a0\u00a0 (D) 1011.
\u00a0
\u00a0Ans: B
\u00a0
Q.78 A register capable of shifting its binary information either to the right or the left is called a<\/strong>
\u00a0(A) parallel register.\u00a0\u00a0 (B) serial register.
\u00a0(C) shift register.\u00a0\u00a0\u00a0\u00a0\u00a0 (D) storage register.
\u00a0
\u00a0Ans: C
\u00a0
Q.79 What is the content of Stack Pointer (SP)?<\/strong>
\u00a0(A)\u00a0 Address of the current instruction \u00a0
\u00a0(B)\u00a0 Address of the next instruction
\u00a0(C) Address of the top element of the stack \u00a0
\u00a0(D) Size of the stack.
\u00a0
\u00a0Ans: C
\u00a0
Q.80 Which of the following interrupt is non maskable<\/strong>
\u00a0(A) INTR.\u00a0\u00a0\u00a0\u00a0\u00a0 (B) RST 7.5.
\u00a0(C) RST 6.5.\u00a0\u00a0 (D) TRAP.
\u00a0
\u00a0Ans: D
\u00a0
Q.81\u00a0 Which of the following is a main memory<\/strong>
\u00a0(A) Secondary memory.\u00a0\u00a0 (B) Auxiliary memory.
\u00a0(C) Cache memory.\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 (D) Virtual memory.
\u00a0
\u00a0Ans: C
\u00a0
Q.82 Which of the following are not a machine instructions<\/strong>
\u00a0(A)\u00a0 MOV.\u00a0\u00a0 (B) ORG.
\u00a0(C) END.\u00a0\u00a0\u00a0 (D) (B) & (C).
\u00a0
\u00a0Ans: D
\u00a0
\u00a0Q.83 In Assembly language programming, minimum number of operands required for an instruction is\/are<\/strong>
\u00a0(A) Zero.\u00a0\u00a0 (B) One.
\u00a0(C) Two.\u00a0\u00a0\u00a0 (D) Both (B) & (C).
\u00a0
\u00a0Ans: A
\u00a0
Q.84\u00a0 The maximum addressing capacity of a micro processor which uses 16 bit database & 32 bit address base is \u00a0<\/strong>
\u00a0(A)\u00a0 64 K.\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 (B) 4 GB.
\u00a0(C) both (A) & (B).\u00a0\u00a0 (D) None of these.
\u00a0
\u00a0Ans: B
\u00a0
Q.85\u00a0 The memory unit that communicates directly with the CPU is called the<\/strong>
\u00a0(A) main memory\u00a0\u00a0\u00a0\u00a0 (B) Secondary memory
\u00a0(C) shared memory\u00a0\u00a0 (D) auxiliary memory.
\u00a0
\u00a0Ans: A
\u00a0
Q.86 The average time required to reach a storage location in memory and obtain its contents is called \u00a0<\/strong>
\u00a0(A) Latency time.\u00a0\u00a0\u00a0\u00a0\u00a0 (B) Access time.
\u00a0(C) Turnaround time.\u00a0\u00a0 (D) Response time.
\u00a0
\u00a0Ans: B
\u00a0
State True or False \u00a0<\/em><\/strong>
\u00a0
Q.87\u00a0\u00a0\u00a0 A byte is a group of 16 bits.<\/strong>
\u00a0
\u00a0 Ans: False \u00a0<\/em>
\u00a0
Q.88\u00a0\u00a0 A nibble is a group of 16 bits.<\/strong>
\u00a0
Ans: False <\/em>\u00a0
\u00a0
Q.89\u00a0\u00a0\u00a0 When a word is to be\u00a0 written in an associative memory, address has got to be given.<\/strong>
\u00a0
Ans: False \u00a0<\/em>
\u00a0
Q.90\u00a0 When two equal numbers are subtracted, the result would be ______and not_________.<\/strong>
\u00a0
\u00a0\u00a0 Ans: +ZERO,\u00a0\u00a0 -ZERO.<\/em><\/p>\n","protected":false},"excerpt":{"rendered":"

Q.76\u00a0 An interface that provides I\/O transfer of data directly to and form the memory unit and peripheral is termed as \u00a0 \u00a0\u00a0 (A) DDA.\u00a0\u00a0 (B) Serial interface. \u00a0\u00a0 (C) BR.\u00a0\u00a0\u00a0 (D) DMA. \u00a0 \u00a0Ans: D \u00a0 Q.77\u00a0 The 2s compliment form (Use 6 bit word) of the number 1010 is \u00a0(A) 111100.\u00a0\u00a0 (B) 110110….<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"footnotes":""},"categories":[18],"tags":[],"class_list":["post-195","post","type-post","status-publish","format-standard","hentry","category-computer-architecture-and-organization"],"_links":{"self":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/posts\/195","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=195"}],"version-history":[{"count":0,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/posts\/195\/revisions"}],"wp:attachment":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=195"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=195"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=195"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}