{"id":196,"date":"2020-04-05T07:08:08","date_gmt":"2020-04-05T07:08:08","guid":{"rendered":"https:\/\/temp.ashkerala.com\/?p=196"},"modified":"2020-04-05T07:08:08","modified_gmt":"2020-04-05T07:08:08","slug":"computer-organization-mcq-7","status":"publish","type":"post","link":"https:\/\/temp.ashkerala.com\/?p=196","title":{"rendered":"Computer Organization MCQ -7"},"content":{"rendered":"

Q.91\u00a0 A ___________development system and an ______are essential tools for writing large assembly language programs.<\/strong>
\u00a0 \u00a0
\u00a0\u00a0 Ans: Microprocessor, assembler<\/em>
\u00a0\u00a0\u00a0\u00a0\u00a0 \u00a0
Q.92\u00a0 In an operation performed by the ALU, carry bit is set to 1 if the end carry C8 is ________. It is cleared to 0 (zero) if the carry is ______\u00a0 _______.
\u00a0<\/strong>
\u00a0\u00a0 Ans: One, zero\u00a0\u00a0\u00a0 \u00a0
\u00a0<\/em>
Choose the correct alternative\u00a0 \u00a0<\/strong><\/em>
\u00a0
Q.93\u00a0 A successive A\/D converter is \u00a0<\/strong>
\u00a0\u00a0 (A)\u00a0 a high-speed converter.\u00a0\u00a0\u00a0 (B)\u00a0\u00a0 a low speed converter.
\u00a0\u00a0 (C)\u00a0 a medium speed converter.\u00a0 (D)\u00a0 none of these.
\u00a0
\u00a0\u00a0 Ans: C
\u00a0
Q.94\u00a0 When necessary, the results are transferred from the CPU to main memory by \u00a0<\/strong>
\u00a0\u00a0 (A) I\/O devices.\u00a0\u00a0\u00a0\u00a0\u00a0 (B) CPU.
\u00a0\u00a0 (C) shift registers.\u00a0 (D)\u00a0 none of these.
\u00a0
\u00a0\u00a0 Ans: B
\u00a0
Q.95\u00a0\u00a0 The gray code equivalent of\u00a0 (1011)_2 is \u00a0<\/strong>
_=Base<\/strong><\/em>
\u00a0\u00a0 (A)\u00a0 1101.\u00a0 (B)\u00a0 1010.
\u00a0\u00a0 (C)\u00a0 1110.\u00a0 (D)\u00a0 1111.
\u00a0
\u00a0\u00a0 Ans: C
\u00a0\u00a0\u00a0\u00a0 \u00a0
Q.96 A combinational logic circuit which sends data coming from a single source to two or more separate destinations is \u00a0<\/strong>
\u00a0 (A)\u00a0\u00a0 Decoder.\u00a0\u00a0\u00a0\u00a0 (B)\u00a0 Encoder.
\u00a0 (C)\u00a0 Multiplexer.\u00a0 (D)\u00a0 Demultiplexer.
\u00a0 \u00a0
\u00a0 Ans: D
\u00a0
Q.97\u00a0 In which addressing mode the operand is given explicitly in the instruction \u00a0<\/strong>
\u00a0 (A)\u00a0 Absolute. (B)\u00a0 Immediate.
\u00a0 (C)\u00a0 Indirect. (D)\u00a0 Direct.
\u00a0
\u00a0 Ans: B
\u00a0\u00a0\u00a0 \u00a0
Q.98 A stack organized computer has<\/strong>
\u00a0\u00a0 (A)\u00a0 Three-address Instruction.\u00a0 (B)\u00a0 Two-address Instruction.
\u00a0\u00a0 (C)\u00a0 One-address Instruction.\u00a0\u00a0\u00a0 (D)\u00a0 Zero-address Instruction.
\u00a0 \u00a0
\u00a0\u00a0 Ans: D
\u00a0
Q.99 A Program Counter contains a number 825 and address part of the instruction contains the number 24. The effective address in the relative address mode, when an instruction\u00a0 is read from the memory is\u00a0 \u00a0<\/strong>
(A)\u00a0 849.\u00a0 (B)\u00a0 850.
(C)\u00a0 801.\u00a0 (D)\u00a0 802.
\u00a0
\u00a0 Ans: B
\u00a0
Q.100\u00a0 A system program that translates and executes an instruction simultaneously is<\/strong>\u00a0 \u00a0
\u00a0 (A)\u00a0 Compiler.\u00a0\u00a0 (B) Interpreter.\u00a0 \u00a0
\u00a0 (C)\u00a0 Assembler.\u00a0 (D) Operating system.\u00a0 \u00a0
\u00a0
\u00a0 Ans: C
\u00a0
Q.101\u00a0 The cache memory of 1K words uses direct mapping with a block size of 4 words.\u00a0 How many blocks can the cache accommodate.<\/strong>
\u00a0 (A)\u00a0 256 words.\u00a0\u00a0 (B)\u00a0 512 words.
\u00a0 (C)\u00a0 1024 words.\u00a0 (D)\u00a0 128 words.
\u00a0
\u00a0 Ans: A
\u00a0
Q.102 A page fault\u00a0\u00a0<\/strong> \u00a0
\u00a0 (A)\u00a0 Occurs when there is an error in a specific page.\u00a0 \u00a0
\u00a0 (B)\u00a0 Occurs when a program accesses a page of main memory.
\u00a0 (C)\u00a0 Occurs when a program accesses a page not currently in main memory. \u00a0
\u00a0 (D)\u00a0 Occurs when a program accesses a page belonging to another program.
\u00a0
\u00a0 Ans: C <\/strong><\/p>\n","protected":false},"excerpt":{"rendered":"

Q.91\u00a0 A ___________development system and an ______are essential tools for writing large assembly language programs. \u00a0 \u00a0 \u00a0\u00a0 Ans: Microprocessor, assembler \u00a0\u00a0\u00a0\u00a0\u00a0 \u00a0 Q.92\u00a0 In an operation performed by the ALU, carry bit is set to 1 if the end carry C8 is ________. It is cleared to 0 (zero) if the carry is ______\u00a0…<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"footnotes":""},"categories":[18],"tags":[],"class_list":["post-196","post","type-post","status-publish","format-standard","hentry","category-computer-architecture-and-organization"],"_links":{"self":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/posts\/196","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=196"}],"version-history":[{"count":0,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/posts\/196\/revisions"}],"wp:attachment":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=196"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=196"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=196"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}