{"id":197,"date":"2020-04-05T07:08:37","date_gmt":"2020-04-05T07:08:37","guid":{"rendered":"https:\/\/temp.ashkerala.com\/?p=197"},"modified":"2020-04-05T07:08:37","modified_gmt":"2020-04-05T07:08:37","slug":"computer-orgenization-mcq-11","status":"publish","type":"post","link":"https:\/\/temp.ashkerala.com\/?p=197","title":{"rendered":"Computer orgenization MCQ -11"},"content":{"rendered":"<p><strong>1) Half adder is an example of ?<\/strong><br \/> a.\u00a0\u00a0\u00a0 Combinational Circuits<br \/> b.\u00a0\u00a0\u00a0 Sequential Circuits<br \/> c.\u00a0\u00a0\u00a0 Asynchronous Circuits<br \/> d.\u00a0\u00a0\u00a0 None of these<br \/> \u00a0<br \/> <strong>Answer = A<\/strong><br \/> Explanation: Combinational circuits are the circuits whose output depends on the inputs of the same instant of time.<\/p>\n<p> <strong>2) In JK flip flop same input, i.e at a particular time or during a clock pulse, the output will oscillate back and forth between 0 and 1. At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0Conversion condition<br \/> b.\u00a0\u00a0 \u00a0Race around condition<br \/> c.\u00a0\u00a0 \u00a0Lock out state<br \/> d.\u00a0\u00a0 \u00a0None of these<br \/> \u00a0<br \/> <strong>Answer = B<\/strong><br \/> Explanation:A race around condition is a flaw in an electronic system or process whereby the output and result of the process is unexpectedly dependent on the sequence or timing of other events.<\/p>\n<p> <strong>3) In a JK flip flop, if j=k, the resulting flip flop is referred to as ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0D flip flop<br \/> b.\u00a0\u00a0 \u00a0T flip flop<br \/> c.\u00a0\u00a0 \u00a0S-R flip flop<br \/> d.\u00a0\u00a0 \u00a0None of these<br \/> \u00a0<br \/> <strong>Answer = C<\/strong><br \/> Explanation: In JK flip flop if both the inputs are same then the flip flop behaves like SR flip flop.<\/p>\n<p> <strong>4) Master slave flip flop is also referred to as ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0Level triggered flip flop<br \/> b.\u00a0\u00a0 \u00a0Pulse triggered flip flop<br \/> c.\u00a0\u00a0 \u00a0Edge triggered flip flop<br \/> d.\u00a0\u00a0 \u00a0None of these<br \/> \u00a0<br \/> <strong>Answer = B<\/strong><br \/> Explanation:The term pulse triggered means the data is entered on the rising edge of the clock pulse, but the output does not reflect the change until the falling edge of clock pulse.<\/p>\n<p> <strong>5) Fetch and decode cycle is required in ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0Direct addressing<br \/> b.\u00a0\u00a0 \u00a0Immediate addressing<br \/> c.\u00a0\u00a0 \u00a0Indirect addressing<br \/> d.\u00a0\u00a0 \u00a0None of above<br \/> \u00a0<br \/> <strong>Answer = B<\/strong><br \/> Explanation:Fetch and decode cycle is required in Immediate addressing because it stores the operand directly on which the operation is performed.<\/p>\n<p> <strong>6) Valid bit in each cache is associated with ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0Each memory byte in cache<br \/> b.\u00a0\u00a0 \u00a0Each memory word in cache<br \/> c.\u00a0\u00a0 \u00a0One bit with the all memory words<br \/> d.\u00a0\u00a0 \u00a0None of above<\/p>\n<p><strong>Answer = D<\/strong><br \/> \u00a0<br \/> <strong>7) In J-K flip flop the function K=J is used to realize ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0D flip flop<br \/> b.\u00a0\u00a0 \u00a0S-R flip flop<br \/> c.\u00a0\u00a0 \u00a0T flip flop<br \/> d.\u00a0\u00a0 \u00a0Master slave flip flop<br \/> \u00a0<br \/> <strong>Answer = D<\/strong><br \/> Explanation: T flip flop allows the same inputs. So if in JK flip flop J = K then it will work as T flip flop.<br \/> \u00a0<br \/> <strong>8) An encoder has 2n input lines and &#8230;.. output lines ?<\/strong><br \/> a.\u00a0\u00a0 \u00a02<br \/> b.\u00a0\u00a0 \u00a0n<br \/> c.\u00a0\u00a0 \u00a02*n<br \/> d.\u00a0\u00a0 \u00a0n*n<br \/> \u00a0<br \/> <strong>Answer = B<\/p>\n<p> 9) ASCII code for alphabet character requires &#8230;.. bits ?<\/strong><br \/> a.\u00a0\u00a0 \u00a016<br \/> b.\u00a0\u00a0 \u00a015<br \/> c.\u00a0\u00a0 \u00a08<br \/> d.\u00a0\u00a0 \u00a07<\/p>\n<p><strong>Answer = D<\/strong><br \/> \u00a0<br \/> <strong>10) The basic limitation of FSM is that ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0An FSM can remember arbitrary large amount of information<br \/> b.\u00a0\u00a0 \u00a0An FSM sometimes recognize grammars that are not regular<br \/> c.\u00a0\u00a0 \u00a0It sometimes fails to recognize grammar that are regular<br \/> d.\u00a0\u00a0 \u00a0All of the above comments are true<br \/> \u00a0<br \/> <strong>Answer = A<\/strong><br \/> Explanation: FSM stands for Finite State Machine.<\/p>\n<p> <strong>11) What is the hexadecimal equivalent of a binary number 10101111 ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0AF<br \/> b.\u00a0\u00a0 \u00a09E<br \/> c.\u00a0\u00a0 \u00a08C<br \/> d.\u00a0\u00a0 \u00a0All of above<br \/> e.\u00a0\u00a0 \u00a0None of above<br \/> \u00a0<br \/> <strong>Answer = A<br \/> \u00a0<br \/> 12) A NOR gate recognizes only the input word whose bits are ?<\/strong><br \/> a.\u00a0\u00a0 \u00a00&#8217;s and 1&#8217;s<br \/> b.\u00a0\u00a0 \u00a01&#8217;s<br \/> c.\u00a0\u00a0 \u00a00&#8217;s<br \/> d.\u00a0\u00a0 \u00a00&#8217;s or 1&#8217;s<br \/> e.\u00a0\u00a0 \u00a0None of above<br \/> \u00a0<br \/> <strong>Answer = C<br \/> \u00a0 \u00a0<br \/> 13) The operation which is commutative but not associative is ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0AND<br \/> b.\u00a0\u00a0 \u00a0OR<br \/> c.\u00a0\u00a0 \u00a0EX-OR<br \/> d.\u00a0\u00a0 \u00a0NAND<br \/> \u00a0<br \/> <strong>Answer = D<br \/> \u00a0 \u00a0<br \/> 14) All digital circuits can be realized using only ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0EX-OR gates<br \/> b.\u00a0\u00a0 \u00a0Half adders<br \/> c.\u00a0\u00a0 \u00a0Multiplexers<br \/> d.\u00a0\u00a0 \u00a0OR gates<br \/> \u00a0<br \/> <strong>Answer = B<br \/> \u00a0 \u00a0<br \/> 15) The XOR gates are ideal for testing parity because even parity words produces a &#8230;&#8230; output and odd parity word produces a &#8230;&#8230;. output ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0low, high<br \/> b.\u00a0\u00a0 \u00a0high, low<br \/> c.\u00a0\u00a0 \u00a0odd, even<br \/> d.\u00a0\u00a0 \u00a0even, odd<br \/> e.\u00a0\u00a0 \u00a0None of above<br \/> \u00a0<br \/> <strong>Answer = A<\/p>\n<p> 16) Flip flop output is always\u00a0 ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0Complementary<br \/> b.\u00a0\u00a0 \u00a0Independent of each other<br \/> c.\u00a0\u00a0 \u00a0the same<br \/> d.\u00a0\u00a0 \u00a0same as inputs<br \/> e.\u00a0\u00a0 \u00a0None of above<br \/> \u00a0<br \/> <strong>Answer = A<br \/> \u00a0 \u00a0<br \/> 17) A half adder adds &#8230;.. bits ?<\/strong><br \/> a.\u00a0\u00a0 \u00a016<br \/> b.\u00a0\u00a0 \u00a010<br \/> c.\u00a0\u00a0 \u00a08<br \/> d.\u00a0\u00a0 \u00a02<br \/> e.\u00a0\u00a0 \u00a0None of above<br \/> \u00a0<br \/> <strong>Answer = D<br \/> \u00a0<br \/> 18) How many flip &#8211; flop circuits are needed to divide by 16 ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0Two<br \/> b.\u00a0\u00a0 \u00a0Four<br \/> c.\u00a0\u00a0 \u00a0Eight<br \/> d.\u00a0\u00a0 \u00a0Sixteen<br \/> \u00a0<br \/> <strong>Answer = C<br \/> \u00a0 \u00a0<br \/> 19) A flip flop is a &#8230;.. elements that stores a 216 binary digits as a low or high voltage ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0chip<br \/> b.\u00a0\u00a0 \u00a0bus<br \/> c.\u00a0\u00a0 \u00a0I\/O<br \/> d.\u00a0\u00a0 \u00a0memory<br \/> e.\u00a0\u00a0 \u00a0None of above<br \/> \u00a0<br \/> <strong>Answer = D<br \/> \u00a0 \u00a0<br \/> 20) A positive AND gate is also a negative ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0NAND gate<br \/> b.\u00a0\u00a0 \u00a0AND gate<br \/> c.\u00a0\u00a0 \u00a0NOR gate<br \/> d.\u00a0\u00a0 \u00a0OR gate<br \/> e.\u00a0\u00a0 \u00a0None of these<br \/> <strong>\u00a0<br \/> Answer = D<br \/> \u00a0 \u00a0<br \/> 21)\u00a0 Which of the following is a minimum error code ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0Octal code<br \/> b.\u00a0\u00a0 \u00a0Binary code<br \/> c.\u00a0\u00a0 \u00a0Gray code<br \/> d.\u00a0\u00a0 \u00a0Excess-3 code<br \/> \u00a0<br \/> <strong>Answer = C<br \/> \u00a0 \u00a0<br \/> 22) In a positive edge triggered JK flip flop, a low J and low K produces ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0High state<br \/> b.\u00a0\u00a0 \u00a0Low state<br \/> c.\u00a0\u00a0 \u00a0toggle state<br \/> d.\u00a0\u00a0 \u00a0no change<br \/> \u00a0<br \/> <strong>Answer = D<\/strong><br \/> Explanation:\u00a0 In JK Flip Flop if J = K = 0 then it holds its current state. There will be no change.<\/p>\n<p> <strong>23)\u00a0 Negative numbers can&#8217;t be represented in ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0signed magnitude form<br \/> b.\u00a0\u00a0 \u00a01&#8217;s complement form<br \/> c.\u00a0\u00a0 \u00a02&#8217;s complement form<br \/> d.\u00a0\u00a0 \u00a0None of above<br \/> \u00a0<br \/> <strong>Answer = D<br \/> \u00a0 \u00a0<br \/> 24) Which of the following architecture is not suitable for realising SIMD ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0Vector processor<br \/> b.\u00a0\u00a0 \u00a0Array processor<br \/> c.\u00a0\u00a0 \u00a0Von Neumann<br \/> d.\u00a0\u00a0 \u00a0All of above<br \/> \u00a0<br \/> <strong>Answer = C<br \/> \u00a0 \u00a0<br \/> 25) The XOR operator + is ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0commutative<br \/> b.\u00a0\u00a0 \u00a0associative<br \/> c.\u00a0\u00a0 \u00a0distributive over AND operator<br \/> d.\u00a0\u00a0 \u00a0A and B<br \/> \u00a0<br \/> <strong>Answer = D<\/strong><br \/> Explanation: As\u00a0 A + B = B + A\u00a0 and\u00a0 A + ( B + C) = (A + B ) + C<br \/> \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Hence it is commutative and associative.<\/p>\n<p> <strong>26)\u00a0 The binary equivalent of the Gray code 11100 is&#8230;.. ?<\/strong><br \/> a.\u00a0\u00a0 \u00a010111<br \/> b.\u00a0\u00a0 \u00a000111<br \/> c.\u00a0\u00a0 \u00a001011<br \/> d.\u00a0\u00a0 \u00a010101<br \/> <strong>\u00a0<br \/> Answer = A<\/strong><br \/> Explanation: The rule for changing the Gray code to binary is that first bit remains the same and the next bit is obtained by adding the first LSB of binary to the second LSB of Gray code and so on&#8230; So the answer of the question is 10111.<\/p>\n<p> <strong>27) An assembler that runs on one machine but produces machine code for another machine is called ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0simulator<br \/> b.\u00a0\u00a0 \u00a0emulator<br \/> c.\u00a0\u00a0 \u00a0cross assembler<br \/> d.\u00a0\u00a0 \u00a0boot strap loader<br \/> \u00a0<br \/> <strong>Answer = C<\/strong><br \/> Explanation:\u00a0 Cross assembler is an assembler which runs on one type of processor and produces machine code for another.<\/p>\n<p> <strong>28) Which of the following unit can be used to measure the speed of a computer ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0SYPS<br \/> b.\u00a0\u00a0 \u00a0MIPS<br \/> c.\u00a0\u00a0 \u00a0BAUD<br \/> d.\u00a0\u00a0 \u00a0FLOPS<br \/> e.\u00a0\u00a0 \u00a0B and D<br \/> \u00a0<br \/> <strong>Answer = E<\/strong><br \/> Explanation:\u00a0 MIPS measures the execution speed of computers CPU but not the whole system. FLOPS is a measure of computer&#8217;s performance especially in the field of scientific calculations that makes heavy use of floating point calculations.<\/p>\n<p> <strong>29)\u00a0 Which of the following logic families is well suited for high speed operations?<\/strong><br \/> a.\u00a0\u00a0 \u00a0TTL<br \/> b.\u00a0\u00a0 \u00a0ECL<br \/> c.\u00a0\u00a0 \u00a0MOS<br \/> d.\u00a0\u00a0 \u00a0CMOS<br \/> \u00a0<br \/> <strong>Answer = B<\/strong><br \/> Explanation: ECL is used for high speed applications because of its price and power demands.<\/p>\n<p> <strong>30) Which of the following comments about half adder are true?<\/strong><br \/> a.\u00a0\u00a0 \u00a0It adds 2 bits<br \/> b.\u00a0\u00a0 \u00a0It is called so because a full adder involves two half adders<br \/> c.\u00a0\u00a0 \u00a0It does half the work of full adder<br \/> d.\u00a0\u00a0 \u00a0It needs two inputs and generates two outputs<br \/> e.\u00a0\u00a0 \u00a0 A, B and D<br \/> \u00a0<br \/> <strong>Answer = E<\/strong><br \/> Explanation:\u00a0 No Explanation<\/p>\n<p> <strong>31) The minimum number of cards to be dealt from an arbitrarily shuffled deck of 52 cards to guarantee that three cards are from some same suit is ?<\/strong><br \/> a.\u00a0\u00a0 \u00a08<br \/> b.\u00a0\u00a0 \u00a03<br \/> c.\u00a0\u00a0 \u00a09<br \/> d.\u00a0\u00a0 \u00a012<br \/> \u00a0<br \/> <strong>Answer = C<\/p>\n<p> 32) Context free languages are closed under ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0union, intersection<br \/> b.\u00a0\u00a0 \u00a0Intersection , complement<br \/> c.\u00a0\u00a0 \u00a0union , kleene star<br \/> d.\u00a0\u00a0 \u00a0Complement , kleene star<br \/> \u00a0<br \/> <strong>Answer = C<\/p>\n<p> 33) Let R be a symmetric and transitive relation on a set A. Then ?<\/strong><br \/> a.\u00a0\u00a0 \u00a0R is reflexive and hence a partial order<br \/> b.\u00a0\u00a0 \u00a0R is reflexive and hence an equivalence relation<br \/> c.\u00a0\u00a0 \u00a0R is not reflexive and hence not an equivalence relation<br \/> d.\u00a0\u00a0 \u00a0None of above<br \/> \u00a0<br \/> <strong>Answer = D<\/strong><\/p>\n","protected":false},"excerpt":{"rendered":"<p>1) Half adder is an example of ? a.\u00a0\u00a0\u00a0 Combinational Circuits b.\u00a0\u00a0\u00a0 Sequential Circuits c.\u00a0\u00a0\u00a0 Asynchronous Circuits d.\u00a0\u00a0\u00a0 None of these \u00a0 Answer = A Explanation: Combinational circuits are the circuits whose output depends on the inputs of the same instant of time. 2) In JK flip flop same input, i.e at a particular time&#8230;<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_kad_post_transparent":"","_kad_post_title":"","_kad_post_layout":"","_kad_post_sidebar_id":"","_kad_post_content_style":"","_kad_post_vertical_padding":"","_kad_post_feature":"","_kad_post_feature_position":"","_kad_post_header":false,"_kad_post_footer":false,"footnotes":""},"categories":[18],"tags":[],"class_list":["post-197","post","type-post","status-publish","format-standard","hentry","category-computer-architecture-and-organization"],"_links":{"self":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/posts\/197","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=197"}],"version-history":[{"count":0,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=\/wp\/v2\/posts\/197\/revisions"}],"wp:attachment":[{"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=197"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=197"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/temp.ashkerala.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=197"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}